1. Field of the Invention
The present invention relates to an audio signal processing apparatus and method. In particular, the present invention relates to an audio signal decoding circuit wherein the information content of the audio signal is compressed.
1. Description of the Related Art
Conventionally, in compressing/expanding systems for a digital audio signal, the so-called standardized MPEG/Audio is available. In the data compressing/expanding according to this standard, the bit system of compressed digital audio signal includes additional information such as a header as well as several samples. In addition, a scheme of expanding the compressed audio-signal (bit stream) is defined in the standardized compressing/expanding system.
There are several schemes in the MPEG/Audio. Here, one of them, Layer I system, will be described below.
According to the Layer I system, information content is compressed in such a manner that a digital audio signal is divided into 32 frequency bands and the number of quantization bits is adequately changed in accordance with digital audio signal.
The number of bits in one frame according to Layer I system is determined by the bit rate and the sampling frequency in accordance with Expression (1): EQU the number of bits in one frame=bits rate *384/sampling frequency(1)
Here, 384 is determined by the number of frequency bands (32) and the number of sample (12), or 12 times 32 makes 384. Accordingly, assuming that the sampling frequency is 32 KHz and the bits rate is 448 Kbps, the number of bits in one frame is 5376 bits.
Referring now to FIG. 1, one frame of Layer I system has additional information such as a header, a CRC (Cyclic Redundancy Check) code, bit allocation indices, scale factor indices and has first through twelfth samples and ancillary data. The header consists ordinarily of 32 bits. The bit allocation indices requires 4 bits per the frequency band and therefore 128 bits for one channel and 256 bits for two channels. In this connection, the header includes a bit which shows the existence of the CRC code and when the CRC code exists, an additional 16 bits are required as CRC code.
In the following description, the number of bits of the scale factor indices and the samples is variable due to the characteristic of the compressed audio signal. When the bit allocation index for each of the frequency bands is not 0, each of the scale factor indices requires 6 bits for each of the frequency bands. In this case, 12 times the number of bits indicated by the bit allocation index of each band is required. This is because 12 samples are included in each of the bands in the direction of time. Therefore, the remainder in subtraction of the aforementioned required number of bits from the total number of bits in one frame is the number of the ancillary data. Ordinary, the ancillary data is negligible information.
Since one frame of the bit-stream is structured as described above, in order to output the first sample of the twelve samples, or the audio signal of the first sample, the total bits of the additional information and the first sample has to be processed within a prescribed time (hereinafter this time is referred to as a unit time). However, in the second sample and the samples after the second sample, only one sample have to be processed within the unit time. Therefore, bias occurs such that the number of bits in the first sample in the frame is larger than the rest of the samples.
In order to realize decoding the aforementioned audio signal, the inventor has designed the first circuit as shown in FIG. 2 as a prototype. In this prototype circuit 100, a bit stream 1 is supplied to and thus temporarily stored in an input buffer 2a. The input buffer 2a outputs a bit stream 5 in response to a request signal 4 from a synchronous detector 3. The synchronous detector 3 detects a synchronous position in a bit stream 5 and generates a synchronous detection signal 12 when a prescribed synchronous signal pattern appears in the header in one frame of the bit stream 1. When the synchronous detection signal 12 is outputted, a code unpacking unit 19 generates a request signal 7 to the input buffer 2a which in turn returns a bit stream 8 to the code unpacking unit 19 in response to the request signal 7. The code unpacking unit 19 unpacks the bit stream 8 into each element and outputs the each element to an unpacking memory 9. Furthermore, the code unpacking unit 19 generates a code unpacking termination signal 22 when the unpacking is completed. A signal processor 10 performs a decoding operation using information stored in the unpacking memory 9 to convert the result into a PCM code 11 and to output the PCM code 11 in a constant interval of time. A timing control unit 20 outputs a control signal 15 and a control signal 21 in response to the synchronous detection signal 12 and the code unpacking termination signal 22 so as to control accesses to the unpacking memory 9 from the signal processor 10 and the code unpacking unit 19 so that they can alternatively in a constant period of time make an access to the unpacking memory 9. Also, an audio sound output unit 25 outputs an audio sound in accordance with the PCM code 11 from the signal processor 10.
Referring now to FIG. 3, this is a timing chart of the prototype circuit 100 shown in FIG. 2. As shown in FIG. 3, responding to the bit stream 1 is inputted into the input buffer 2a at a constant period, the synchronous detector 3 outputs a request signal 4. When the synchronous detector 3 detects the synchronous position in the header, the synchronous detector 3 outputs the synchronous detection signal 12 and stops the request signal 4. Accordingly, the code unpacking unit 19 outputs and the request signal 7 in response to the synchronous detection signal 12. Thus, the code unpacking unit 19 is supplied the additional information and the first sample. Then, the code unpacking unit 19 unpacks the first sample in accordance with the bit allocation indices and outputs the first sample and scale factor indices to the unpacking memory 9. At this moment, the code unpacking unit 19 stops the request signal 7 and outputs the code unpacking termination signal 22. The operation of the code unpacking unit 19 is represented in FIG. 3 as CODE UNPACKING. Next, the timing control unit 20 outputs the control signal 15 in response to the code unpacking termination signal 22 only when dealing with the first sample in the first frame. This control signal 15 causes the signal processor 10 to start signal-processing. After the first sample, the timing control unit 20 controls the timing of both the code unpacking unit 19 and the signal processor 10 by outputting the control signal 15 and the control signal 21 respectively, for allowing them to alternatively operate on the unpacking memory 9 up to the twelfth sample at fixed intervals of time. In short, the timing control unit 20 controls both a period of CODE UNPACKING and SIGNAL PROCESSING.
After completing the operation to the twelfth sample, the ancillary data is read from the input buffer 2a.
Up to here is the description of the operation for the first frame. Following frames after the second are processed in the same manner.
At the first, the inventor assumes that the input buffer 2a has a capacity of one frame. Because, a general circuit for MPEG/Audio has been processing in a unit of one frame. Therefore, in order to generally design the circuit, the capacity of the input buffer 2a is applied the amount of one frame.
Referring now to FIGS. 4 and 5, there are circuit diagram of another prototype circuit 200 and a timing chart of the circuit 200, in which the same constituents as those shown in FIGS. 2 and 3 are denoted by the same reference numerals or symbols.
The status at the start time of signal-processing on the first sample in the first frame in the prototype circuit 200 will be described below.
To begin with, the bit stream 1 is supplied with the input buffer 2a. Therefore, the synchronous detector 3 generates the synchronous detection signal 12 in order to synchronize for each part of the circuit 200. Then, the code unpacking unit 19 unpacks the first sample. However, the input buffer 2a had accumulated the number of bits of one frame before the signal processor 10 had begun to decode. Accordingly, the timing control unit 20 generating the control signal 15 had to wait until the period of 12 ms with the sampling frequency of 32 KHz, or that of one frame, from a point of rising down of request signal 7. For this reason, a counter 16 counts to the period of one frame in response to the code unpacking termination signal 22 from the code unpacking unit 19. The counter 16 counts a clock, e.g. a master clock for the digital audio processor. When the count is finally over, the counter 16 generates an operation restart signal 18 to the timing control unit 20. The timing control unit 20 had reserved to generate the control signal 15 until a generation of the operation restart signal 18.
At the start time of signal-processing, the number of bits of the second frame stored in the input buffer 2a is the same as the number of bits of the additional information in the first frame and that of the first sample.
Thus, when the sum of the number of bits of additional information in the second frame and that of the first sample is larger than the sum of the number of bits of the additional information in the first frame and that of the first sample, the additional information in the second frame and that of the first sample are not completely inputted to the input buffer 2a. For this cause, if the above-processing continues, the signal processor 10 may give off an unnecessary sound owing to insufficient data read out of the unpacking memory 9.
Therefore, in order to prevent the unnecessary sound from occurring, it is required that a sufficiency capacity in the input buffer 2a, e.g. 1.5 frames.
However, since the prototype circuit as described above needs an input buffer with a capacity of the total number of bits in one frame or more to store a bit stream temporarily, there are disadvantages in that the scale of processing circuit becomes large and its cost becomes high.
Further, the timing control circuit 20 waits to generate the control signal 15 as long as the counter 16 counts to the period of one frame. Therefore, the start time of signal-processing is late.